FIFOs are used in a variety of circuit applications. For example, data communication circuits use FIFO structures to address different system timing requirements. A serializer, for example, employs an internal clock that may not be synchronized with an external clock used to supply data to the circuit. A FIFO is used to transfer the data from the external clock regime to the internal clock regime. Typically, such a FIFO includes a number of registers that operate in response to a write pointer and a read pointer. An external clock usually provides or controls the write pointer while an internal clock controls the read pointer. Even though the phase relationship between these two clock domains is arbitrary, conventional FIFO designs require the frequencies of the two clock signals to be the same. There are applications, however, that require one clock domain to be of different frequency compared to the other (e.g., the write clock frequency be half that of the read clock, or vice versa). Furthermore, FIFOs require additional control circuitry to ensure the correct timing relationship between the write pointers and the read pointers. For example, the FIFO pointers must be set to the correct initial positions upon start-up, and then reset when any one of a number of conditions occur (e.g., overflow, loss of write clock, etc.). Also, FIFO pointers need to be monitored for a number of different purposes including detection of overflow conditions, detection of loss of external (write) clock, abnormalities in pointer operation, etc.
There is a need for improved method and circuitry for implementing high speed FIFO structures that meet all of the above requirements.